1. Field of the Invention
The embodiments disclosed herein relate to modeling parasitic capacitances associated with a diffusion region of a silicon-on-insulator (SOI) device and, more particularly, to a method, a computer system, and a program storage device for modeling parasitic capacitances associated with a diffusion region (e.g., diffusion region to substrate capacitance and diffusion region to adjacent diffusion region capacitance) as a function of the distance between the diffusion region and the adjacent diffusion region(s).
2. Description of the Related Art
Parasitic capacitances associated with a diffusion region of a silicon-on-insulator (SOI) device (e.g., a source/drain region of a metal oxide semiconductor field effect transistor (MOSFET), a diffusion region of a metal oxide semiconductor (MOS) capacitor, etc.) can include, for example, the capacitance between that diffusion region and the substrate below as well as capacitances between that diffusion region and any adjacent conductive structures (e.g., any adjacent diffusion regions of other SOI devices). Such parasitic capacitances can greatly impact SOI device performance. Thus, during SOI device design, accurate modeling of parasitic capacitances associated with each diffusion region is very important. However, the current techniques used to model may result in error. Therefore, there is a need in the art for a technique that can be used to more accurately model the parasitic capacitances associated with each diffusion region of an SOI device.